What is metastability in digital circuits, and how is it mitigated in flip-flops and other synchronous elements?

Metastability occurs when a flip-flop or latch enters an undefined state due to timing violations at the input. It can lead to unpredictable behavior and data loss. Techniques such as adding synchronization stages, using higher-speed flip-flops, and increasing setup and hold times help mitigate metastability and improve circuit reliability.